1. Field of the Invention
The embodiments disclosed herein relate to field effect transistors and, more particularly, to a field effect transistor structure with silicon source/drain regions and, for optimal charge-carrier mobility and band energy, a silicon alloy channel region positioned laterally between the silicon source/drain regions.
2. Description of the Related Art
A hetero-structure P-type metal oxide semiconductor field effect transistor (MOSFET) typically incorporates a semiconductor body comprising a stack of silicon (Si) and silicon germanium (SiGe) layers. A gate structure is formed on a center portion of the stack and a P-type dopant (e.g., boron) is implanted into end portions of the stack so as to form the channel region and source/drain regions, respectively. The added silicon germanium in the channel region provides for greater hole mobility in the channel region and also allows the valence-band energy of the P-type MOSFET to be selectively adjusted (e.g., up to 300 millielectron volts (meV)) for device design optimization. Unfortunately, while the added silicon germanium can be beneficial, the diffusivity of boron through silicon germanium is quite low, thereby making an operable P-type MOSFET with an exclusively silicon germanium channel region heretofore unattainable. More specifically, prior attempts to make operable P-type MOSFETs with exclusively silicon germanium channel regions have failed because the low diffusivity of boron through silicon germanium introduces poor source/drain junction profiles, which in turn cause undesirable “short-channel effects”, such as drain induced barrier lowering (DIBL) and a reduction in threshold voltage (Vt), also referred to as sub-threshold voltage swing.